SH7206 Datasheet, PDF (592/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
TGRA_3
TCDR
Bit WRE = 1
Bit SCC = 1
MTU2-MTU2S
synchronous clearing
TGRB_3
TCNT_3
(MTU2S)
TCNT_4
(MTU2S)
TDDR
H'0000
Positive phase
Counters
are cleared
Negative phase
Output waveform is active-low.
Initial value output
is suppressed.
Figure 10.67 Example of Synchronous Clearing in Interval Tb at Trough
(Timing (11) in Figure 10.56; Bit WRE is 1 and Bit SCC is 1 in TWCR of MTU2S)
Rev. 3.00 Jun. 18, 2008 Page 568 of 1160
REJ09B0191-0300