SH7206 Datasheet, PDF (865/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
Initial
Bit
Bit Name Value R/W Description
15
ADF
0
R/(W)* A/D End Flag
Status flag indicating the end of A/D conversion.
[Clearing conditions]
• Cleared by reading ADF while ADF = 1, then writing
0 to ADF
• Cleared when DMAC is activated by ADI interrupt
and ADDR is read
[Setting conditions]
• A/D conversion ends in single mode
• A/D conversion ends for the selected channels in
multi mode
• A/D conversion ends for the selected channels in
scan mode
14
ADIE
0
R/W A/D Interrupt Enable
Enables or disables the interrupt (ADI) requested at the
end of A/D conversion. Set the ADIE bit while A/D
conversion is not being made.
0: A/D end interrupt request (ADI) is disabled
1: A/D end interrupt request (ADI) is enabled
13
ADST
0
R/W A/D Start
Starts or stops A/D conversion. This bit remains set to 1
during A/D conversion.
0: A/D conversion is stopped
1: Single mode: A/D conversion starts. This bit is
automatically cleared to 0 when A/D conversion ends
on the selected channel.
Multi mode: A/D conversion starts. This bit is
automatically cleared to 0 when A/D conversion is
completed cycling through the selected channels.
Scan mode: A/D conversion starts. A/D conversion is
continuously performed until this bit is cleared to 0 by
software, by a power-on reset, or by a transition to
software standby mode or module standby mode.
12

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Jun. 18, 2008 Page 841 of 1160
REJ09B0191-0300