SH7206 Datasheet, PDF (718/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Pins
MTU2 channel 0 pins
(PE1/TIOC0B)
MTU2 channel 0 pins
(PE2/TIOC0C)
MTU2 channel 0 pins
(PE3/TIOC0D)
Conditions
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Input level detection or
SPOER setting
Detailed Conditions
MTU2PE1ZE •
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE2ZE •
((POE8F • POE8E) + (MTU2CH0HIZ))
MTU2PE3ZE •
((POE8F • POE8E) + (MTU2CH0HIZ))
12.4.1 Input Level Detection Operation
If the input conditions set by ICSR1 to ICSR3 occur on the POE0 to POE8 pins, the high-current
pins and the pins for channel 0 of the MTU2 are placed in high-impedance state. Note however,
that these high-current and MTU2 pins enter high-impedance state only when general input/output
function, MTU2 function, or MTU2S function is selected for these pins.
(1) Falling Edge Detection
When a change from a high to low level is input to the POE0 to POE8 pins, the high-current pins
and the pins for channel 0 of the MTU2 are placed in high-impedance state.
Figure 12.2 shows the sample timing after the level changes in input to the POE0 to POE8 pins
until the respective pins enter high-impedance state.
Pφ
POE input
PE9/
TIOC3B
Pφ rising edge
Falling edge detection
High-impedance state
Note: The other high-current pins and MTU2 channel 0 pins also enter the high-impedance state in the similar timing.
Figure 12.2 Falling Edge Detection
Rev. 3.00 Jun. 18, 2008 Page 694 of 1160
REJ09B0191-0300