SH7206 Datasheet, PDF (1174/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
25.4.3 Bus Timing
Table 25.8 Bus Timing
Page Revision (See Manual for Details)
1080
to
1082
Table amended.
Item
Chip enable setup time
WAIT setup time
WAIT hold time
Address setup time for AH
DACK, TEND delay time
Symbol
tCS
tWTS
tWTH
tAVVH
tDACD
Bφ = 66.66MHz*⁴
Min.
Max.
0

1/2tcyc + 7.5 
Unit Figure
ns _{Figures 25.12 to}
25.15, 25.20
ns Figures 25.13 to
25.20, 25.41, 25.43
1/2tcyc + 3.5 
ns _{Figures 25.13 to}
25.20, 25.41, 25.43
1/2tcyc - 2
Refer to
peripheral
modules

ns
Refer to ns
peripheral
modules
Figures 25.16
Figures 25.12 to
25.34, 25.38, 25.40
to 25.43
1082 Note added.
Note:
4. 1/2 tcyc indicated in minimum and maximum
values for the item of delay, setup, and hold
times represents a half cycle from the rising
edge with a clock. That is, 1/2 tcyc describes
a reference of the falling edge with a clock.
Figure 25.12 Basic Bus Timing for 1083 Figure amended.
Normal Space (No Wait)
t_CSD1
t_CSD1
CSn
tCS
Figure 25.13 Basic Bus Timing for 1084 Figure amended.
Normal Space (One Software Wait
Cycle)
t_CSD1
t_CSD1
CSn
t_CS
Figure 25.14 Basic Bus Timing for 1085 Figure amended.
Normal Space (One External Wait
Cycle)
t_CSD1
t_CSD1
CSn
t_CS
Rev. 3.00 Jun. 18, 2008 Page 1150 of 1160
REJ09B0191-0300