SH7206 Datasheet, PDF (193/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 User Break Controller (UBC)
Bit
5
4 to 0
Bit Name
PCB0

Initial
Value
0
All 0
R/W
R/W
R
Description
PC Break Select 0
Selects the break timing of the instruction fetch cycle
for channel 0 as before or after instruction execution.
0: PC break of channel 0 is generated before
instruction execution
1: PC break of channel 0 is generated after instruction
execution
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Jun. 18, 2008 Page 169 of 1160
REJ09B0191-0300