SH7206 Datasheet, PDF (1157/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Appendix
Pin Function
Pin State
Reset State
Power-Down State
Type
Pin Name
Power-On*⁷
Area 0 Data Bus Width
8 Bits 16 Bits 32 Bits
Software
Manual Standby
Sleep
Bus
Mastership
Release
I/O port PE16, PE15 to PE11*⁵,
Z
PE10, PE9*⁵,
PE8 to PE0
I/O
K/Z*¹
I/O
I/O
PF7 to PF0
Z
I
Z
I
I
[Legend]
I: Input
O: Output
H: High-level output
L: Low-level output
Z: High-impedance
K: Input pins become high-impedance, and output pins retain their state.
Notes: 1. Controlled by the HIZ bit in standby control register 3 (STBCR3) (see section 22,
Power-Down Modes).
2. Controlled by the HIZCNT bit in the common control register of the BSC (see section 8,
Bus State Controller (BSC)).
3. Controlled by the HIZMEM bit in the common control register of the BSC (see section 8,
Bus State Controller (BSC)).
4. Z when the TAP controller of the H-UDI is neither the Shift-DR nor Shift-IR state.
5. High-impedance control through POE2 (see section 12, Port Output Enable 2 (POE2)).
6. The EXTAL pin must be fixed (pulled up/pulled down/connected to power
supply/connected to ground) and the XTAL pin must be open.
7. Power-on reset by low-level input to the RES pin. The pin states after a power-on reset
by the H-UDI reset assert command or WDT overflow are the same as the initial pin
states at normal operation (see section 19, Pin Function Controller (PFC)).
8. These are the pin states in product chip mode (ASEMD = H). See the Emulation
Manual for the pin states in ASE mode (ASEMD = L).
Rev. 3.00 Jun. 18, 2008 Page 1133 of 1160
REJ09B0191-0300