SH7206 Datasheet, PDF (147/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
5.3.7 PINT Interrupt Request Register (PIRR)
PIRR is a 16-bit register that indicates interrupt requests from external input pins PINT7 to
PINT0. PIRR is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
8
7
6
5
4
3
2
1
0
- PINT7R PINT6R PINT5R PINT4R PINT3R PINT2R PINT1R PINT0R
0
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
R
Bit
15 to 8
Bit Name

7
PINT7R
6
PINT6R
5
PINT5R
4
PINT4R
3
PINT3R
2
PINT2R
1
PINT1R
0
PINT0R
[Legend]
n = 7 to 0
Initial
Value
All 0
0
0
0
0
0
0
0
0
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R PINT Interrupt Request
R These bits indicate the status of the PINT7 to PINT0
R
interrupt requests.
R
0: No interrupt request at PINTn pin
R
1: Interrupt request at PINTn pin
R
R
R
Rev. 3.00 Jun. 18, 2008 Page 123 of 1160
REJ09B0191-0300