SH7206 Datasheet, PDF (432/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
(2) and, in case that the setting is one of the following three cases
• Write-Write cycles (IWW[2:0]) >=001
• Read-Read cycles in the same spaces (IWRRS[2:0]) >=001
• External Wait Mask Specification (WM) =0
In addition to above condition, DREQ sampling and access type is one of the following two cases,
DREQ can be sampled twice.
• For DREQ level detection: only write access
• For DREQ edge detection: both write access and read access
Figures 9.19 to 9.22 show DREQ sampling timing for above access.
For the external access as shown above conditions, please use one of the following three ways.
• For DREQ edge detection: please input one DREQ edge at maximum in that external access.
• For DREQ level detection in overrun 0: please negate DREQ after the detection of the first
DACK negation and before the second DACK negation.
• For DREQ level detection in overrun 1: please negate DREQ after the detection of the first
DACK assertion and before the second DACK assertion.
Rev. 3.00 Jun. 18, 2008 Page 408 of 1160
REJ09B0191-0300