SH7206 Datasheet, PDF (222/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Cache
7.4.4 Notes
1. Programs that access memory-mapped cache of the operand cache should be placed in a cache-
disabled space. Programs that access memory-mapped cache of the instruction cache should be
placed in a cache-disabled space, and in each of the beginning and the end of that, two or more
read accesses to on-chip peripheral modules or external address space (cache-disabled address)
should be executed.
2. Rewriting the address array contents so that two or more ways are hit simultaneously is
prohibited. Operation is not guaranteed if the address array contents are changed so that two or
more ways are hit simultaneously.
3. Memory-mapped cache can be accessed only by the CPU and not by the DMAC. Registers can
be accessed by the CPU and the DMAC.
Rev. 3.00 Jun. 18, 2008 Page 198 of 1160
REJ09B0191-0300