SH7206 Datasheet, PDF (182/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 User Break Controller (UBC)
Figure 6.1 shows a block diagram of the UBC.
Access
control
I bus
IDB IAB
C bus
MDB MAB FAB
Access
comparator
Address
comparator
Data
comparator
Channel 0
Access
comparator
Address
comparator
Data
comparator
Channel 1
Control
BBR_0
BAR_0
BAMR_0
BDR_0
BDMR_0
I bus
BBR_1
BAR_1
BAMR_1
BDR_1
BDMR_1
BRCR
[Legend]
BBR: Break bus cycle register
BAR: Break address register
BAMR: Break address mask register
User break interrupt request
UBCTRG pin output
BDR: Break data register
BDMR: Break data mask registe
BRCR: Break control register
Figure 6.1 Block Diagram of UBC
Rev. 3.00 Jun. 18, 2008 Page 158 of 1160
REJ09B0191-0300