SH7206 Datasheet, PDF (1180/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

N
NMI interrupt.......................................... 127
Noise filter .............................................. 824
Nonlinearity error ................................... 857
Normal space interface ........................... 267
Note on bypass capacitor.......................... 86
Note on using a PLL oscillation circuit .... 86
Note on using an external crystal
resonator ................................................... 85
O
Offset error ............................................. 857
On-chip peripheral module interrupts..... 129
On-chip peripheral module request ........ 389
On-chip RAM......................................... 975
Operation in asynchronous mode ........... 766
Operation in clocked synchronous
mode ....................................................... 777
Output load circuit ................................ 1125
P
Package................................................. 1134
Package dimensions.............................. 1135
Page conflict ........................................... 976
PCMCIA interface.................................. 330
Permissible signal source impedance ..... 860
Pin arrangement.......................................... 8
Pin function controller (PFC) ................. 871
Pin states of this LSI............................. 1129
PINT interrupts....................................... 128
PLL circuit 1............................................. 71
PLL circuit 2............................................. 71
POE2 interrupt source ............................ 697
POE2 module timing ............................ 1118
Port output enable 2 (POE2)................... 667
Power-down mode.................................. 316
Power-down modes ................................ 977
Power-down state ..................................... 68
Rev. 3.00 Jun. 18, 2008 Page 1156 of 1160
REJ09B0191-0300
Power-on reset .......................................... 94
Power-on sequence ................................. 317
Prefetch operation
(only for operand cache) ......................... 190
Procedure register (PR)............................. 32
Processing of analog input pins .............. 859
Product code ......................................... 1134
Program counter (PC) ............................... 32
Program execution state............................ 68
PWM Modes ........................................... 519
Q
Quantization error ................................... 857
R
Receive data sampling timing and
receive margin (asynchronous mode) ..... 789
Register addresses (by functional
module, in order of the corresponding
section numbers) ................................... 1006
Register bank error exception
handling ............................................ 99, 153
Register bank errors .................................. 99
Register bank exception.......................... 153
Register banks................................... 33, 149
Register bits .......................................... 1021
Register states in each operating
mode ..................................................... 1052
Registers
ACKEYR............................................ 262
ACSWR .............................................. 261
ADCR ................................................. 844
ADCSR ............................................... 840
ADDRA to ADDRH ........................... 839
BAMR................................................. 162
BAR .................................................... 161
BBR .................................................... 165
BDMR................................................. 164