SH7206 Datasheet, PDF (510/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name value R/W Description
0
OLS1P
0
R/W Output Level Select 1P*
This bit selects the output level on TIOC3B in reset-
synchronized PWM mode/complementary PWM mode.
See table 10.38.
Note: * Setting the TOCS bit in TOCR1 to 1 makes this bit setting valid.
Table 10.32 Setting of Bits BF1 and BF0
Bit 7
BF1
0
0
Bit 6
BF0
0
1
1
0
1
1
Description
Complementary PWM Mode
Reset-Synchronized PWM Mode
Does not transfer data from the Does not transfer data from the
buffer register (TOLBR) to TOCR2. buffer register (TOLBR) to TOCR2.
Transfers data from the buffer
Transfers data from the buffer
register (TOLBR) to TOCR2 at the register (TOLBR) to TOCR2 when
crest of the TCNT_4 count.
TCNT_3/TCNT_4 is cleared
Transfers data from the buffer
Setting prohibited
register (TOLBR) to TOCR2 at the
trough of the TCNT_4 count.
Transfers data from the buffer
register (TOLBR) to TOCR2 at the
crest and trough of the TCNT_4
count.
Setting prohibited
Table 10.33 TIOC4D Output Level Select Function
Bit 5
Function
Compare Match Output
OLS3N Initial Output Active Level Up Count
Down Count
0
High level
Low level
High level
Low level
1
Low level
High level
Low level
High level
Note: The reverse phase waveform initial output value changes to the active level after elapse of
the dead time after count start.
Rev. 3.00 Jun. 18, 2008 Page 486 of 1160
REJ09B0191-0300