SH7206 Datasheet, PDF (633/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Pφ
TCNT
input clock
TCNT
(underflow)
Underflow
signal
TCFU flag
H'0000
H'FFFF
TCIU interrupt
Figure 10.114 TCIU Interrupt Setting Timing
(4) Status Flag Clearing Timing
After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DMAC is
activated, the flag is cleared automatically. Figures 10.115 and 116 show the timing for status flag
clearing by the CPU, and figure 10.117 shows the timing for status flag clearing by the DMAC.
TSR write cycle
T1
T2
Pφ
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 10.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
Rev. 3.00 Jun. 18, 2008 Page 609 of 1160
REJ09B0191-0300