SH7206 Datasheet, PDF (14/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

8.6.3 Burst MPX-I/O Interface ...................................................................................... 355
Section 9 Direct Memory Access Controller (DMAC)..................................... 357
9.1 Features.............................................................................................................................. 357
9.2 Input/Output Pins............................................................................................................... 360
9.3 Register Descriptions......................................................................................................... 361
9.3.1 DMA Source Address Registers (SAR)................................................................ 365
9.3.2 DMA Destination Address Registers (DAR)........................................................ 366
9.3.3 DMA Transfer Count Registers (DMATCR) ....................................................... 367
9.3.4 DMA Channel Control Registers (CHCR) ........................................................... 368
9.3.5 DMA Reload Source Address Registers (RSAR)................................................. 376
9.3.6 DMA Reload Destination Address Registers (RDAR)......................................... 377
9.3.7 DMA Reload Transfer Count Registers (RDMATCR) ........................................ 378
9.3.8 DMA Operation Register (DMAOR) ................................................................... 379
9.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3).................. 383
9.4 Operation ........................................................................................................................... 385
9.4.1 Transfer Flow........................................................................................................ 385
9.4.2 DMA Transfer Requests ....................................................................................... 387
9.4.3 Channel Priority.................................................................................................... 391
9.4.4 DMA Transfer Types............................................................................................ 394
9.4.5 Number of Bus Cycles and DREQ Pin Sampling Timing .................................... 403
9.5 Usage Notes ....................................................................................................................... 407
9.5.1 Setting of the Half-End Flag and Generation of the Half-End Interrupt............... 407
9.5.2 Timing of DACK and TEND Outputs .................................................................. 407
9.5.3 DREQ Sampling ................................................................................................... 407
Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)................................... 413
10.1 Features.............................................................................................................................. 413
10.2 Input/Output Pins............................................................................................................... 419
10.3 Register Descriptions......................................................................................................... 420
10.3.1 Timer Control Register (TCR).............................................................................. 424
10.3.2 Timer Mode Register (TMDR)............................................................................. 428
10.3.3 Timer I/O Control Register (TIOR)...................................................................... 431
10.3.4 Timer Compare Match Clear Register (TCNTCMPCLR).................................... 450
10.3.5 Timer Interrupt Enable Register (TIER)............................................................... 451
10.3.6 Timer Status Register (TSR)................................................................................. 456
10.3.7 Timer Buffer Operation Transfer Mode Register (TBTM)................................... 464
10.3.8 Timer Input Capture Control Register (TICCR)................................................... 465
10.3.9 Timer Synchronous Clear Register (TSYCR) ...................................................... 466
10.3.10 Timer A/D Converter Start Request Control Register (TADCR) ......................... 468
Rev. 3.00 Jun. 18, 2008 Page xiv of xxiv