SH7206 Datasheet, PDF (1168/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
10.3.5 Timer Interrupt Enable
Register (TIER)
10.3.6 Timer Status Register
(TSR)
10.5.3 A/D Converter Activation
(3) A/D Converter Activation by
A/D Converter Start Request
Delaying Function
Page Revision (See Manual for Details)
455 • TIER_5
Description of bit 1 amended.
(Before) Enables or disables interrupt requests
(TGIV_5) by compare match between TCNTV_5 and
TGRV_5. →
(After) Enables or disables interrupt requests (TGIV_5)
by the CMFV5 bit when the CMFV5 bit in TSR_5 is set
to 1.
455 • TIER_5
Description of bit 0 amended.
(Before) Enables or disables interrupt requests
(TGIW_5) by compare match between TCNTW_5 and
TGRW_5. →
(After) Enables or disables interrupt requests (TGIW_5)
by the CMFW5 bit when the CMFW5 bit in TSR_5 is
set to 1.
461, • TSR_5
462 _{Description of bits 2 and 1 amended.}
… input capture or compare match. Only 0 can be
written, for flag clearing.
[Setting condition]
• When TCNTV_5 value is transferred to TGRV_5
and TGRV_5 is functioning as a register for
measuring the pulse width of the external input
signal. The transfer timing is specified by the IOC
bits in timer I/O control registers U_5, V_5, and
W_5 (TIORU_5, TIORV_5, and TIORW_5).*²
598 Description amended.
The A/D converter can be activated by generating A/D
converter start request signal TRG4AN or TRG4BN
when the TCNT_4 count matches the TADCORA or
TADCORB value if the UT4AE, DT4AE, UT4BE, or
DT4BE bit in the A/D converter start request control
register (TADCR) is set to 1 …
Rev. 3.00 Jun. 18, 2008 Page 1144 of 1160
REJ09B0191-0300