SH7206 Datasheet, PDF (371/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Table 8.19 Minimum Number of Idle Cycles on Internal Bus (CPU Operation)
Clock Ratio (Iφ:Bφ)
CPU Operation
8:1
6:1
4:1
3:1
2:1
1:1
Write → write
1
1
2
2
2
3
Write → read
0
0
0
0
0
1
Read → write
1
1
2
2
2
3
Read → read
0
0
0
0
0
1
Table 8.20 Minimum Number of Idle Cycles on Internal Bus (DMAC Operation)
Transfer Mode
DMAC Operation Dual Address
Single Address
Write → write
0
2
Write → read
0 or 2
0
Read → write
0
0
Read → read
0
2
Notes: 1. The write → write and read → read columns in dual address transfer indicate the cycles
in the divided access cycles.
2. For the write → read cycles in dual address transfer, 0 means different channels are
activated successively and 2 means when the same channel is activated successively.
3. The write → read and read → write columns in single address transfer indicate the case
when different channels are activated successively. The "write" means transfer from a
device with DACK to external memory and the "read" means transfer from external
memory to a device with DACK.
Rev. 3.00 Jun. 18, 2008 Page 347 of 1160
REJ09B0191-0300