SH7206 Datasheet, PDF (513/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
Figure 10.3 shows an example of the PWM output level setting procedure in buffer operation.
Set bit TOCS
Set TOCR2
Set TOLBR
[1]
[1] Set bit TOCS in TOCR1 to 1 to enable the TOCR2 setting.
[2] Use bits BF1 and BF0 in TOCR2 to select the TOLBR buffer
transfer timing. Use bits OLS3N to OLS1N and OLS3P to OLS1P
to specify the PWM output levels.
[2]
[3] The TOLBR initial setting must be the same value as specified in
bits OLS3N to OLS1N and OLS3P to OLS1P in TOCR2.
[3]
Figure 10.3 PWM Output Level Setting Procedure in Buffer Operation
10.3.23 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode. These
register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Bit: 7
-
Initial value: 1
R/W: R
6
BDC
0
R/W
5
N
0
R/W
4
P
0
R/W
3
FB
0
R/W
2
WF
0
R/W
1
VF
0
R/W
0
UF
0
R/W
Initial
Bit
Bit Name value R/W Description
7
—
1
R
Reserved
This bit is always read as 1. The write value should
always be 1.
6
BDC
0
R/W Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
Rev. 3.00 Jun. 18, 2008 Page 489 of 1160
REJ09B0191-0300