SH7206 Datasheet, PDF (534/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
10.4.3 Buffer Operation
Buffer operation, provided for channels 0, 3, and 4, enables TGRC and TGRD to be used as buffer
registers. In channel 0, TGRF can also be used as a buffer register.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or as a compare match register.
Note: TGRE_0 cannot be designated as an input capture register and can only operate as a
compare match register.
Table 10.43 shows the register combinations used in buffer operation.
Table 10.43 Register Combinations in Buffer Operation
Channel
0
3
4
Timer General Register
TGRA_0
TGRB_0
TGRE_0
TGRA_3
TGRB_3
TGRA_4
TGRB_4
Buffer Register
TGRC_0
TGRD_0
TGRF_0
TGRC_3
TGRD_3
TGRC_4
TGRD_4
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 10.14.
Compare match signal
Buffer
register
Timer general
register
Comparator
TCNT
Figure 10.14 Compare Match Buffer Operation
Rev. 3.00 Jun. 18, 2008 Page 510 of 1160
REJ09B0191-0300