SH7206 Datasheet, PDF (98/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Clock Pulse Generator (CPG)
3.3 Clock Operating Modes
Table 3.2 shows the relationship between the combinations of the mode control pins (MD_CLK2
and MD_CLK0) and the clock operating modes. Table 3.3 shows the usable frequency ranges in
the clock operating modes.
Table 3.2 Clock Operating Modes
Pin Values
Mode MD_CLK2 MD_CLK0
2
0
0
7
1
1
Clock I/O
PLL Circuit 2 PLL Circuit 1
Source
Output On/Off
On/Off
CKIO Frequency
EXTAL or
CKIO
crystal resonator
ON (×4)
ON (×1, 2, 3, 4) (EXTAL or crystal
resonator) ×4
CKIO

OFF
ON (×1, 2, 3, 4, (CKIO)
6, 8)
• Mode 2
The frequency of the signal received from the EXTAL pin or crystal resonator LSI is
quadrupled by the PLL circuit 2 before it is supplied as the clock signal. This enables to use
the external clock of lower frequency. Either a crystal resonator with a frequency in the range
from 10 to 16.67 MHz or an external signal in the same frequency range input on the EXTAL
pin may be used. The frequency range of CKIO is from 40 to 66.67 MHz.
• Mode 7
In mode 7, the CKIO pin functions as an input pin and draws an external clock signal. The
PLL circuit 1 shapes its waveform and the setting of the frequency control register multiplies
its frequency before the clock enters the LSI. For reduced current and hence power
consumption, fix (pull up/pull down/connect to power supply/connect to ground) the EXTAL
pin and open the XTAL pin when the LSI is used in mode 7.
Rev. 3.00 Jun. 18, 2008 Page 74 of 1160
REJ09B0191-0300