SH7206 Datasheet, PDF (812/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
15.6.3 Restriction on DMAC Usage
1. When the DMAC writes data to SCFTDR due to a TXI interrupt request, the state of the
TEND flag becomes undefined. Therefore, the TEND flag should not be used as the transfer
end flag in such a case.
2. When a channel is being used in full-duplex transmission, in which the DMAC is on the
transmit side and the CPU on the receive side, the RDF or DR flag in the serial status register
(SCFSR) could be cleared after these flags are set and receive data is read from the receive
FIFO data register (SCFRDR).
3. When a channel is being used in full-duplex transmission, in which the DMAC is on the
receive side and the CPU on the transmit side, the TDFE or TEND flag in the serial status
register (SCFSR) could be cleared after these flags are set and transmit data is written to the
transmit FIFO data register (SCFTDR).
15.6.4 Break Detection and Processing
Break signals can be detected by reading the RxD pin directly when a framing error (FER) is
detected. In the break state the input from the RxD pin consists of all 0s, so the FER flag is set and
the parity error flag (PER) may also be set.
Note that, although transfer of receive data to SCFRDR is halted in the break state, the SCIF
receiver continues to operate.
15.6.5 Sending a Break Signal
The I/O condition and level of the TxD pin are determined by the SPB2IO and SPB2DT bits in the
serial port register (SCSPTR). This feature can be used to send a break signal.
Until TE bit is set to 1 (enabling transmission) after initializing, the TxD pin does not work.
During the period, mark status is performed by the SPB2DT bit. Therefore, the SPB2IO and
SPB2DT bits should be set to 1 (high level output).
To send a break signal during serial transmission, clear the SPB2DT bit to 0 (designating low
level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the
transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD
pin.
Rev. 3.00 Jun. 18, 2008 Page 788 of 1160
REJ09B0191-0300