SH7206 Datasheet, PDF (297/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 8.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
Wait states inserted
by WAIT signal
T1
Tw
Tw
Twx
T2
Read
Write
CKIO
A25 to A0
CSn
RD/WR
RD
D31 to D0
WEn
D31 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.10 Wait Cycle Timing for Normal Space Access
(Wait Cycle Insertion Using WAIT Signal)
Rev. 3.00 Jun. 18, 2008 Page 273 of 1160
REJ09B0191-0300