SH7206 Datasheet, PDF (830/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 I²C Bus Interface 3 (IIC3)
Initial
Bit
Bit Name Value R/W Description
2
AL/OVE
0
R/W Arbitration Lost Flag/Overrun Error Flag
Indicates that arbitration was lost in master mode with
the I²C bus format and that the final bit has been
received while RDRF = 1 with the clocked synchronous
format.
When two or more master devices attempt to seize the
bus at nearly the same time, if the I²C bus interface 3
detects data differing from the data it sent, it sets AL to
1 to indicate that the bus has been occupied by another
master.
[Clearing condition]
• When 0 is written in AL/OVE after reading AL/OVE
=1
[Setting conditions]
• If the internal SDA and SDA pin disagree at the rise
of SCL in master transmit mode
• When the SDA pin outputs high in master mode
while a start condition is detected
• When the final bit is received with the clocked
synchronous format while RDRF = 1
1
AAS
0
R/W Slave Address Recognition Flag
In slave receive mode, this flag is set to 1 if the first
frame following a start condition matches bits SVA[6:0]
in SAR.
[Clearing condition]
• When 0 is written in AAS after reading AAS = 1
[Setting conditions]
• When the slave address is detected in slave receive
mode
• When the general call address is detected in slave
receive mode.
0
ADZ
0
R/W General Call Address Recognition Flag
This bit is valid in slave receive mode with the I²C bus
format.
[Clearing condition]
• When 0 is written in ADZ after reading ADZ = 1
[Setting condition]
• When the general call address is detected in slave
receive mode
Rev. 3.00 Jun. 18, 2008 Page 806 of 1160
REJ09B0191-0300