SH7206 Datasheet, PDF (733/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT
Even when the count-up occurs in the T2 cycle while writing to CMCNT in words, the writing has
priority over the count-up. In this case, the count-up is not performed. Figure 13.6 shows the
timing to write to CMCNT in words.
Peripheral clock
(Pφ)
Address signal
Internal write signal
CMCSR write cycle
T1
T2
CMCNT
CMCNT count-up
enable signal
CMCNT
N
M
Figure 13.6 Conflict between Word-Write and Count-Up Processes of CMCNT
Rev. 3.00 Jun. 18, 2008 Page 709 of 1160
REJ09B0191-0300