SH7206 Datasheet, PDF (1021/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 High-Performance User Debugging Interface (H-UDI)
Section 23 High-Performance User Debugging Interface
(H-UDI)
This LSI incorporates a high-performance user debugging interface (H-UDI) for emulator support.
23.1 Features
The high-performance user debugging interface (H-UDI) has reset and interrupt request functions.
The H-UDI in this LSI is used for emulator connection. Refer to the emulator manual for the
method of connecting the emulator.
Figure 23.1 shows a block diagram of the H-UDI.
TDI
SDBPR
SDIR
TDO
MUX
TCK
TMS
TRST
TAP control circuit
Decoder
Local
bus
[Legend]
SDBPR:
SDIR:
Bypass register
Instruction register
Figure 23.1 Block Diagram of H-UDI
Rev. 3.00 Jun. 18, 2008 Page 997 of 1160
REJ09B0191-0300