SH7206 Datasheet, PDF (103/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 3 Clock Pulse Generator (CPG)
3.4.1 Frequency Control Register (FRQCR)
FRQCR is a 16-bit readable/writable register used to specify whether a clock is output from the
CKIO pin in software standby mode, the frequency multiplication ratio of PLL circuit 1, and the
frequency division ratio of the internal clock and peripheral clock (Pφ). Only word access can be
used on FRQCR.
FRQCR is initialized to H'1003 only by a power-on reset. FRQCR retains its previous value by a
manual reset or in software standby mode. The previous value is also retained when an internal
reset is triggered by an overflow of the WDT.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
- CKOEN -
STC[2:0]
-
IFC[2:0]
RNGS
PFC[2:0]
Initial value: 0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
R/W: R
R
R R/W R R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 13 
12
CKOEN
Initial
Value
All 0
1
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Clock Output Enable
Specifies whether a clock is output from the CKIO pin,
or whether the CKIO pin is placed in the level-fixed
state during standby mode or cancellation of standby
mode.
If this bit is cleared to 0, the CKIO pin is fixed at low
during standby mode or cancellation of standby
mode. Therefore, the malfunction of an external circuit
because of an unstable CKIO clock during
cancellation of standby mode can be prevented. In
clock operating mode 7, the CKIO pin functions as an
input regardless of this bit value.
0: The CKIO pin is fixed to the low level during
standby mode or cancellation of standby mode.
(Clock is output during the period other than
standby mode or cancellation of standby mode.)
1: Clock is output from CKIO pin (placed in the high-
impedance state during standby mode).
Rev. 3.00 Jun. 18, 2008 Page 79 of 1160
REJ09B0191-0300