SH7206 Datasheet, PDF (11/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

4.7 When Exception Sources Are Not Accepted ..................................................................... 106
4.8 Stack Status after Exception Handling Ends...................................................................... 107
4.9 Usage Notes ....................................................................................................................... 109
4.9.1 Value of Stack Pointer (SP) .................................................................................. 109
4.9.2 Value of Vector Base Register (VBR) .................................................................. 109
4.9.3 Address Errors Caused by Stacking of Address Error Exception Handling ......... 109
Section 5 Interrupt Controller (INTC) ...............................................................111
5.1 Features.............................................................................................................................. 111
5.2 Input/Output Pins ............................................................................................................... 113
5.3 Register Descriptions ......................................................................................................... 114
5.3.1 Interrupt Priority Registers 01, 02, 05 to 14 (IPR01, IPR02, IPR05 to IPR14) .... 115
5.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 117
5.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 118
5.3.4 Interrupt Control Register 2 (ICR2)...................................................................... 119
5.3.5 IRQ Interrupt Request Register (IRQRR)............................................................. 120
5.3.6 PINT Interrupt Enable Register (PINTER)........................................................... 122
5.3.7 PINT Interrupt Request Register (PIRR) .............................................................. 123
5.3.8 Bank Control Register (IBCR).............................................................................. 124
5.3.9 Bank Number Register (IBNR) ............................................................................ 125
5.4 Interrupt Sources................................................................................................................ 127
5.4.1 NMI Interrupt........................................................................................................ 127
5.4.2 User Break Interrupt ............................................................................................. 127
5.4.3 H-UDI Interrupt .................................................................................................... 127
5.4.4 IRQ Interrupts ....................................................................................................... 128
5.4.5 PINT Interrupts ..................................................................................................... 128
5.4.6 On-Chip Peripheral Module Interrupts ................................................................. 129
5.5 Interrupt Exception Handling Vector Table and Priority................................................... 130
5.6 Operation ........................................................................................................................... 139
5.6.1 Interrupt Operation Sequence ............................................................................... 139
5.6.2 Stack after Interrupt Exception Handling ............................................................. 142
5.7 Interrupt Response Time.................................................................................................... 143
5.8 Register Banks ................................................................................................................... 149
5.8.1 Banked Register and Input/Output of Banks ........................................................ 150
5.8.2 Bank Save and Restore Operations....................................................................... 150
5.8.3 Save and Restore Operations after Saving to All Banks....................................... 152
5.8.4 Register Bank Exception....................................................................................... 153
5.8.5 Register Bank Error Exception Handling ............................................................. 153
5.9 Data Transfer with Interrupt Request Signals .................................................................... 154
Rev. 3.00 Jun. 18, 2008 Page xi of xxiv