SH7206 Datasheet, PDF (280/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Bit
8
7 to 5
4, 3
2
1, 0
Bit Name
BACTV
Initial
Value
0

All 0
A3ROW[1:0] 00

0
A3COL[1:0] 00
R/W Description
R/W Bank Active Mode
Specifies to access whether in auto-precharge mode
(using READA and WRITA commands) or in bank
active mode (using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT
commands)
Note:
Bank active mode can be used only when
either the upper or lower bits of the CS3 space
are used. When both the CS2 and CS3
spaces are set to SDRAM, specify the auto-
precharge mode.
R
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W Number of Bits of Row Address for Area 3
Specify the number of bits of the row address for
area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
R
Reserved
This bit is always read as 0. The write value should
always be 0.
R/W Number of Bits of Column Address for Area 3
Specify the number of bits of the column address for
area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
Rev. 3.00 Jun. 18, 2008 Page 256 of 1160
REJ09B0191-0300