SH7206 Datasheet, PDF (580/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(m) Counter Clearing by Another Channel
In complementary PWM mode, by setting a mode for synchronization with another channel by
means of the timer synchronous register (TSYR), and selecting synchronous clearing with bits
CCLR2 to CCLR0 in the timer control register (TCR), it is possible to have TCNT_3, TCNT_4,
and TCNTS cleared by another channel.
Figure 10.55 illustrates the operation.
Use of this function enables counter clearing and restarting to be performed by means of an
external signal.
TGRA_3
TCDR
TCNT_3
TCNT_4
TDDR
H'0000
Channel 1
Input capture A
TCNTS
TCNT_1
Synchronous counter clearing by channel 1 input capture A
Figure 10.55 Counter Clearing Synchronized with Another Channel
Rev. 3.00 Jun. 18, 2008 Page 556 of 1160
REJ09B0191-0300