SH7206 Datasheet, PDF (713/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit
Bit Name
Value R/W Description
13
MTU2P2CZE 1
R/W* MTU2 Port 2 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PE12/TIOC4A and PE14/TIOC4C
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE2F,
POE3F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
12
MTU2P3CZE 1
R/W* MTU2 Port 3 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PE13/TIOC4B and PE15/TIOC4D
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE2F,
POE3F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
11
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
10
MTU2SP1CZE 1
R/W* MTU2S Port 1 High-Impedance Disable
This bit should be cleared to 0 when any of bits 6 to 4
and 2 to 0 in POECR2 is set to enable output
comparison and high impedance. Otherwise, the pin
state may be affected.
9
MTU2SP2CZE 1
R/W* MTU2S Port 2 High-Impedance Disable
This bit should be cleared to 0 when any of bits 6 to 4
and 2 to 0 in POECR2 is set to enable output
comparison and high impedance. Otherwise, the pin
state may be affected.
Rev. 3.00 Jun. 18, 2008 Page 689 of 1160
REJ09B0191-0300