SH7206 Datasheet, PDF (712/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
Initial
Bit
Bit Name
Value R/W Description
0
MTU2PE0ZE 0
R/W* MTU2 PE0 High-Impedance Enable
Specifies whether to place the PE0/TIOC0A pin for
channel 0 in the MTU2 in high-impedance state when
either POE8F or MTU2CH0HIZ bit is set to 1.
0: Does not place the pin in high-impedance state
1: Places the pin in high-impedance state
12.3.8 Port Output Enable Control Register 2 (POECR2)
POECR2 is a 16-bit readable/writable register that controls high-impedance state of the pins.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
MTU2 MTU2 MTU2
P1CZE P2CZE P3CZE
-
MTU2S MTU2S MTU2S
P1CZE P2CZE P3CZE
-
MTU2S MTU2S MTU2S
P4CZE P5CZE P6CZE
-
MTU2S MTU2S MTU2S
P7CZE P8CZE P9CZE
Initial value: 0
1
1
1
0
1
1
1
0
0
0
0
0
0
0
0
R/W: R R/W* R/W* R/W* R R/W* R/W* R/W* R R/W* R/W* R/W* R R/W* R/W* R/W*
Note: * Can be modified only once after a power-on reset.
Initial
Bit
Bit Name
Value R/W Description
15
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
14
MTU2P1CZE 1
R/W* MTU2 Port 1 Output Comparison/High-Impedance
Enable
Specifies whether to compare output levels for the
MTU2 high-current PE9/TIOC3B and PE11/TIOC3D
pins and to place them in high-impedance state when
the OSF1 bit is set to 1 while the OCE1 bit is 1 or
when any one of the POE0F, POE1F, POE2F,
POE3F, and MTU2CH34HIZ bits is set to 1.
0: Does not compare output levels or place the pins in
high-impedance state
1: Compares output levels and places the pins in
high-impedance state
Rev. 3.00 Jun. 18, 2008 Page 688 of 1160
REJ09B0191-0300