SH7206 Datasheet, PDF (136/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 5 Interrupt Controller (INTC)
Figure 5.1 shows a block diagram of the INTC.
IRQOUT
NMI
IRQ7 to IRQ0
PINT7 to PINT0
UBC
H-UDI
DMAC
CMT
BSC
WDT
MTU2
MTU2S
POE2
ADC
IIC3
SCIF
Input control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
Priority
identifier
Com-
parator
Interrupt
request
SR
I3 I2 I1 I0
CPU
ICR0
ICR2
PINTER
IBCR
ICR1
IRQRR
PIRR
IBNR
IPR
IPR01, IPR02,
IPR05 to IPR14
Module bus
Bus
interface
INTC
[Legend]
UBC: User break controller
ICR0:
Interrupt control register 0
H-UDI: High-performance user debugging interface ICR1:
Interrupt control register 1
DMAC: Direct memory access controller
ICR2:
Interrupt control register 2
CMT: Compare match timer
IRQRR:
IRQ interrupt request register
BSC: Bus state controller
PINTER:
PINT interrupt enable register
WDT: Watchdog timer
PIRR:
PINT interrupt request register
MTU2: Multi-function timer pulse unit 2
IBCR:
Bank control register
MTU2S: Multi-function timer pulse unit 2S
IBNR:
Bank number register
POE2: Port output enable 2
IPR01, IPR02, IPR05 to IPR14: Interrupt priority registers 01, 02,
ADC: A/D converter
IIC3: I2C bus interface 3
05 to 14
SCIF: Serial communication interface with FIFO
Figure 5.1 Block Diagram of INTC
Rev. 3.00 Jun. 18, 2008 Page 112 of 1160
REJ09B0191-0300