SH7206 Datasheet, PDF (348/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Bus Width Access Size CSnWCR. BST[1:0] Bits Number of Bursts Access Count
32 bits
8 bits
Not affected
1
1
16 bits
Not affected
1
1
32 bits
Not affected
1
1
16 bytes
Not affected
4
1
Note: * When the bus width is 16 bits, the access size is 16 bits, and the BST[1:0] bits in
CSnWCR are 10, the number of bursts and access count depend on the access start
address. At address H'xxx0 or H'xxx8, 4-4 burst access is performed. At address H'xxx4
or H'xxxC, 2-4-2 burst access is performed.
CKIO
A25 to A0
T1 Tw Tw T2B Twb T2B Twb T2B Twb T2
CSn
RD/WR
RD
D31 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 8.36 Burst ROM Access Timing (Clocked Asynchronous)
(Bus Width = 32 Bits, 16-Byte Transfer (Number of Burst 4), Wait Cycles Inserted in First
Access = 2, Wait Cycles Inserted in Second and Subsequent Access Cycles = 1)
Rev. 3.00 Jun. 18, 2008 Page 324 of 1160
REJ09B0191-0300