SH7206 Datasheet, PDF (706/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
12.3.4 Output Level Control/Status Register 2 (OCSR2)
OCSR2 is a 16-bit readable/writable register that controls the enable/disable of both output level
comparison and interrupts, and indicates status.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
OSF2 -
-
-
-
- OCE2 OIE2 -
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/(W)*¹ R
R
R
R
R R/W*² R/W R
R
R
R
R
R
R
R
Notes: 1. Only 0 can be written to clear the flag after 1 is read.
2. Can be modified only once after a power-on reset.
Initial
Bit
Bit Name Value
15
OSF2 0
14 to 10 
All 0
9
OCE2 0
R/W Description
R/(W)*¹ Output Short Flag 2
Indicates that any one of the three pairs of MTU2S 2-
phase outputs to be compared has simultaneously
become an active level.
[Clearing condition]
• By writing 0 to OSF2 after reading OSF2 = 1
[Setting condition]
• When any one of the three pairs of 2-phase outputs
has simultaneously become an active level
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W*² Output Short High-Impedance Enable 2
Specifies whether to place the pins in high-impedance
state when the OSF2 bit in OCSR2 is set to 1.
0: Does not place the pins in high-impedance state
1: Places the pins in high-impedance state
Rev. 3.00 Jun. 18, 2008 Page 682 of 1160
REJ09B0191-0300