SH7206 Datasheet, PDF (22/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

20.6.3 Port E Port Registers H, L (PEPRH, PEPRL)....................................................... 969
20.7 Port F ................................................................................................................................. 971
20.7.1 Register Descriptions............................................................................................ 971
20.7.2 Port F Data Register (PFDR) ................................................................................ 972
20.8 Usage Notes ....................................................................................................................... 974
Section 21 On-Chip RAM ................................................................................. 975
21.1 Features.............................................................................................................................. 975
21.2 Usage Notes ....................................................................................................................... 976
21.2.1 Page Conflict ........................................................................................................ 976
21.2.2 RAME and RAMWE Bits .................................................................................... 976
Section 22 Power-Down Modes........................................................................ 977
22.1 Features.............................................................................................................................. 977
22.1.1 Power-Down Modes ............................................................................................. 977
22.2 Register Descriptions......................................................................................................... 979
22.2.1 Standby Control Register (STBCR)...................................................................... 980
22.2.2 Standby Control Register 2 (STBCR2)................................................................. 981
22.2.3 Standby Control Register 3 (STBCR3)................................................................. 982
22.2.4 Standby Control Register 4 (STBCR4)................................................................. 984
22.2.5 System Control Register 1 (SYSCR1) .................................................................. 986
22.2.6 System Control Register 2 (SYSCR2) .................................................................. 988
22.3 Operation ........................................................................................................................... 990
22.3.1 Sleep Mode ........................................................................................................... 990
22.3.2 Software Standby Mode........................................................................................ 990
22.3.3 Software Standby Mode Application Example..................................................... 993
22.3.4 Module Standby Function..................................................................................... 994
22.4 Usage Notes ....................................................................................................................... 995
22.4.1 Note on Writing to Registers ................................................................................ 995
Section 23 High-Performance User Debugging Interface (H-UDI)................. 997
23.1 Features.............................................................................................................................. 997
23.2 Input/Output Pins............................................................................................................... 998
23.3 Register Descriptions......................................................................................................... 999
23.3.1 Bypass Register (SDBPR) .................................................................................... 999
23.3.2 Instruction Register (SDIR) .................................................................................. 999
23.4 Operation ......................................................................................................................... 1001
23.4.1 TAP Controller ................................................................................................... 1001
23.4.2 Reset Configuration ............................................................................................ 1002
23.4.3 TDO Output Timing ........................................................................................... 1002
Rev. 3.00 Jun. 18, 2008 Page xxii of xxiv