SH7206 Datasheet, PDF (184/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 User Break Controller (UBC)
6.3 Register Descriptions
The UBC has the following registers. Five control registers for each channel and one common
control register for channel 0 and channel 1 are available. A register for each channel is described
as BAR_0 for the BAR register in channel 0.
Table 6.2 Register Configuration
Channel Register Name
0
Break address register_0
Break address mask register_0
Break bus cycle register_0
Break data register_0
Break data mask register_0
1
Break address register_1
Break address mask register_1
Break bus cycle register_1
Break data register_1
Break data mask register_1
Common Break control register
Abbrevia-
tion
R/W
BAR_0
R/W
BAMR_0 R/W
BBR_0
R/W
BDR_0
R/W
BDMR_0 R/W
BAR_1
R/W
BAMR_1 R/W
BBR_1
R/W
BDR_1
R/W
BDMR_1 R/W
BRCR
R/W
Initial Value
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'00000000
H'00000000
H'0000
H'00000000
H'00000000
H'00000000
Address
Access
Size
H'FFFC0400 32
H'FFFC0404 32
H'FFFC04A0 16
H'FFFC0408 32
H'FFFC040C 32
H'FFFC0410 32
H'FFFC0414 32
H'FFFC04B0 16
H'FFFC0418 32
H'FFFC041C 32
H'FFFC04C0 32
Rev. 3.00 Jun. 18, 2008 Page 160 of 1160
REJ09B0191-0300