SH7206 Datasheet, PDF (430/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
CKIO
T1 T2 Taw T1 T2
Address
CS
RD
Data
WEn
DACKn
(Active low)
TEND
(Active low)
WAIT
Note: TEND is asserted for the last unit of DMA transfer. If a transfer unit
is divided into multiple bus cycles and the CS is negated between
the bus cycles, TEND is also divided.
Figure 9.18 BSC Normal Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 3.00 Jun. 18, 2008 Page 406 of 1160
REJ09B0191-0300