SH7206 Datasheet, PDF (116/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 4 Exception Handling
Exception Sources
Vector
Numbers
Vector Table Address Offset
Integer division exception
(division by zero)
17
H'00000044 to H'00000047
Integer division exception (overflow) 18
H'00000048 to H'0000004B
(Reserved by system)
19
H'0000004C to H'0000004F
:
:
31
H'0000007C to H'0000007F
Trap instruction (user vector)
32
H'00000080 to H'00000083
:
:
63
H'000000FC to H'000000FF
External interrupts (IRQ, PINT),
64
on-chip peripheral module interrupts* _:
H'00000100 to H'00000103
:
511
H'000007FC to H'000007FF
Note: * The vector numbers and vector table address offsets for each external interrupt and on-
chip peripheral module interrupt are given in table 5.4 in section 5, Interrupt Controller
(INTC).
Table 4.4 Calculating Exception Handling Vector Table Addresses
Exception Source
Vector Table Address Calculation
Resets
Vector table address = (vector table address offset)
= (vector number) × 4
Address errors, register bank Vector table address = VBR + (vector table address offset)
errors, interrupts, instructions
= VBR + (vector number) × 4
Notes: 1. Vector table address offset: See table 4.3.
2. Vector number: See table 4.3.
Rev. 3.00 Jun. 18, 2008 Page 92 of 1160
REJ09B0191-0300