SH7206 Datasheet, PDF (721/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Port Output Enable 2 (POE2)
12.5 Interrupts
The POE2 issues a request to generate an interrupt when the specified condition is satisfied during
input level detection or output level comparison. Table 12.5 shows the interrupt sources and their
conditions.
Table 12.5 Interrupt Sources and Conditions
Name
OEI1
OEI2
OEI3
Interrupt Source
Output enable interrupt 1
Output enable interrupt 2
Output enable interrupt 3
Interrupt Flag
POE0F, POE1F, POE2F,
POE3F, and OSF1
POE8F
POE4F, POE5F, POE6F,
POE7F, and OSF2
Condition
PIE1 • (POE0F + POE1F +
POE2F + POE3F) + OIE1 •
OSF1
PIE3 • POE8F
PIE2 • (POE4F + POE5F +
POE6F + POE7F) + OIE2 •
OSF2
Rev. 3.00 Jun. 18, 2008 Page 697 of 1160
REJ09B0191-0300