SH7206 Datasheet, PDF (407/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 9 Direct Memory Access Controller (DMAC)
9.3.9 DMA Extension Resource Selectors 0 to 3 (DMARS0 to DMARS3)
The DMA extension resource selectors (DMARS) are 16-bit readable/writable registers that
specify the DMA transfer sources from peripheral modules in each channel. DMARS0 is for
channels 0 and 1, DMARS1 is for channels 2 and 3, DMARS2 is for channels 4 and 5, and
DMARS3 is for channels 6 and 7. Table 9.4 shows the specifiable combinations.
DMARS can specify transfer requests from eight SCIF sources, two IIC3 sources, two A/D
converter sources, five MTU2 sources, and two CMT sources.
DMARS is initialized to H'00000000 by a power-on reset and retains the value in manual reset,
software standby mode, and module standby mode.
• DMARS0
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH1 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH1 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH0 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH0 RID[1:0]
0
0
R/W R/W
• DMARS1
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH3 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH3 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH2 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH2 RID[1:0]
0
0
R/W R/W
• DMARS2
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH5 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH5 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH4 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH4 RID[1:0]
0
0
R/W R/W
• DMARS3
Bit:
Initial value:
R/W:
15
0
R/W
14
0
R/W
13 12
CH7 MID[5:0]
0
0
R/W R/W
11
0
R/W
10
0
R/W
9
8
CH7 RID[1:0]
0
0
R/W R/W
7
0
R/W
6
0
R/W
5
4
3
CH6 MID[5:0]
0
0
0
R/W R/W R/W
2
0
R/W
1
0
CH6 RID[1:0]
0
0
R/W R/W
Transfer requests from the various modules specify MID and RID as shown in table 9.4.
Rev. 3.00 Jun. 18, 2008 Page 383 of 1160
REJ09B0191-0300