SH7206 Datasheet, PDF (626/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Multi-Function Timer Pulse Unit 2 (MTU2)
(4) Timing for Counter Clearing by Compare Match/Input Capture
Figures 10.100 and 101 show the timing when counter clearing on compare match is specified,
and figure 10.102 shows the timing when counter clearing on input capture is specified.
Pφ
Compare
match signal
Counter
clear signal
TCNT
N
H'0000
TGR
N
Figure 10.100 Counter Clear Timing (Compare Match) (Channels 0 to 4)
Pφ
Compare
match signal
Counter
clear signal
TCNT
N-1
H'0000
TGR
N
Figure 10.101 Counter Clear Timing (Compare Match) (Channel 5)
Rev. 3.00 Jun. 18, 2008 Page 602 of 1160
REJ09B0191-0300