SH7206 Datasheet, PDF (1167/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
9.5.1 Setting of the Half-End Flag 407
and Generation of the Half-End
Interrupt
Added
9.5.2 Timing of DACK and TEND 407 Added
Outputs
9.5.3 DREQ Sampling
407, Added
408
Figure 9.19 Example of DREQ
Input Detection in Cycle Steal
Mode Edge Detection when
DACK is Split to 4 Due to Idia
Cycles
409 Added
Figure 9.20 Example of DREQ
Input Detection in Cycle Steal
Mode Edge Detection when
DACK is Split to 2 Due to Idia
Cycles
409 Added
Figure 9.21 Example of DREQ
Input Detection in Cycle Steal
Mode Level Detection when
DACK is Split to 4 Due to Idia
Cycles
410 Added
Figure 9.22 Example of DREQ
Input Detection in Cycle Steal
Mode Level Detection when
DACK is Split to 2 Due to Idia
Cycles
411 Added
10.1 Features
415 Channel 5 of DMAC activation amended.
Table 10.1 MTU2 Functions
(Before) TGR compare match or input capture →
(After) —
10.3.5 Timer Interrupt Enable
Register (TIER)
455 • TIER_5
Description of bit 2 amended.
(Before) Enables or disables interrupt requests
(TGIU_5) by compare match between TCNTU_5 and
TGRU_5. →
(After) Enables or disables interrupt requests (TGIU_5)
by the CMFU5 bit when the CMFU5 bit in TSR_5 is set
to 1.
Rev. 3.00 Jun. 18, 2008 Page 1143 of 1160
REJ09B0191-0300