SH7206 Datasheet, PDF (850/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 I²C Bus Interface 3 (IIC3)
Master receive mode
Clear TEND in ICSR
Clear TRS in ICCR1 to 0
Clear TDRE in ICSR
Clear ACKBT in ICIER to 0
Dummy-read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Last receive ^Yes
- 1?
No
Read ICDRR
Set ACKBT in ICIER to 1
Set RCVD in ICCR1 to 1
Read ICDRR
Read RDRF in ICSR
No
RDRF=1 ?
Yes
Clear STOP in ICSR
Write 0 to BBSY
and SCP
Read STOP in ICSR
No
STOP=1 ?
Yes
Read ICDRR
Clear RCVD in ICCR1 to 0
[1] Clear TEND, select master receive mode, and then clear TDRE. *
[2] Set acknowledge to the transmit device. *
[1]
[3] Dummy-read ICDDR. *
[2]
[4] Wait for 1 byte to be received
[5] Check whether it is the (last receive - 1).
[3]
[6] Read the receive data.
[4]
[7] Set acknowledge of the final byte. Disable continuous reception (RCVD = 1).
[8] Read the (final byte - 1) of received data.
[5]
[9] Wait for the last byte to be receive.
[10] Clear the STOP flag.
[6]
[11] Issue the stop condition.
[12] Wait for the creation of stop condition.
[7]
[13] Read the last byte of receive data.
[14] Clear RCVD.
[8]
[15] Set slave receive mode.
Notes: * Make sure that no interrupt will be generated during steps [1] to [3].
[9]
When the size of receive data is only one byte in reception,
steps [2] to [6] are skipped after step [1], before jumping to step [7].
The step [8] is dummy-read in ICDRR.
[10]
[11]
[12]
[13]
[14]
Clear MST in ICCR1 to 0
[15]
End
Figure 16.19 Sample Flowchart for Master Receive Mode
Rev. 3.00 Jun. 18, 2008 Page 826 of 1160
REJ09B0191-0300