SH7206 Datasheet, PDF (857/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 I²C Bus Interface 3 (IIC3)
16.7 Usage Notes
16.7.1 Note on Issue of Stop/Start Conditions
Issue the stop condition or start (re-transmit) condition after recognizing the falling edge of the
ninth clock. The falling edge of the ninth clock can be recognized by checking the SCLO bit in the
I²C control register 2 (ICCR2). Note that if the stop condition or start (re-transmit) condition is
issued in a particular timing and the situations shown below, these conditions may not correctly
output. No problem will occur otherwise.
1. The rising edge of the SCL becomes less sharp and longer due to the SCL bus load (load
capacitor and pull-up resistor) than the period defined in section 16.6, Bit Synchronous Circuit.
2. When the slave device elongates the low level period between the eighth and ninth clocks and
activates the bit synchronous circuit.
16.7.2 Settings for Multi-Master Operation
In multi-master operation, when the setting for IIC transfer rate (ICCR1.CKS[3:0]) makes this LSI
slower than the other masters, pulse cycles with an unexpected length will infrequently be output
on SCL.
Be sure to specify a transfer rate that is at least 1/1.8 of the fastest transfer rate among the other
masters.
16.7.3 Note on Master Receive Mode
Reading ICDRR around the falling edge of the 8th clock might fail to fetch the receive data.
In addition, when RCVD is set to 1 around the falling edge of the 8th clock and the receive buffer
is full, a stop condition may not be issued.
Use either 1 or 2 below as a measure against the situations above.
1. In master receive mode, read ICDRR before the rising edge of the 8th clock.
2. In master receive mode, set the RCVD bit to 1 so that transfer proceeds in byte units.
Rev. 3.00 Jun. 18, 2008 Page 833 of 1160
REJ09B0191-0300