SH7206 Datasheet, PDF (1173/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Item
Page Revision (See Manual for Details)
24.3 Register States in Each
Operating Mode
1056 Settings in software standby mode in MTU2 and
to MTU2S amended.
1061 _{(Before) Initialized →}
(After) Retained
25.3 DC Characteristics
1069 Table amended.
Table 25.3 DC Characteristics (1)
[Common Items]
Item
Input leakage
current
All input pins (except
PB2, PB3)
PB2, PB3
Symbol Min. Typ. Max. Unit Test Conditions
|Iin |

 1.0
µA
Vin =
0.5 to PVCC - 0.5 V

 1.0
µA
25.4.2 Control Signal Timing
Table 25.7 Control Signal Timing
1077 Table amended.
Item
BREQ setup time
BREQ hold time
BACK delay time
Bus buffer off time 1
Bus buffer off time 2
Bus buffer on time 1
Bus buffer on time 2
BACK setup time for bus buffer off
Symbol
tBREQS
tBREQH
tBACKD
tBOFF1
tBOFF2
tBON1
tBON2
tBACKS
Bφ = 66.67MHz
Min.
Max.
1/2tcyc + 7

Unit
Figure
ns
Figure 25.11
1/2tcyc + 2

ns

1/2tcyc + 13
ns

15
ns

15
ns

15
ns

15
ns
0

ns
Figure 25.11 Bus Release Timing 1079 Figure amended.
25.4.3 Bus Timing
Table 25.8 Bus Timing
BACK
A25 to A0,
D31 to D0
RD, RD/WR,
RASU/L,
CASU/L,
CSn, WEn,
BS, CKE
t_BACKD
t_BACKS
t_BOFF1
t_BOFF2
1080 Table condition amended.
Conditions: Clock mode 2/7, PVCC = 3.0 V to 3.6 V,
PVSS = 0 V, Ta = -20°C to +85°C
Rev. 3.00 Jun. 18, 2008 Page 1149 of 1160
REJ09B0191-0300