SH7206 Datasheet, PDF (17/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

11.2 Register Descriptions ......................................................................................................... 664
Section 12 Port Output Enable 2 (POE2) ..........................................................667
12.1 Features.............................................................................................................................. 668
12.2 Input/Output Pins ............................................................................................................... 670
12.3 Register Descriptions ......................................................................................................... 672
12.3.1 Input Level Control/Status Register 1 (ICSR1) .................................................... 673
12.3.2 Output Level Control/Status Register 1 (OCSR1) ................................................ 677
12.3.3 Input Level Control/Status Register 2 (ICSR2) .................................................... 678
12.3.4 Output Level Control/Status Register 2 (OCSR2) ................................................ 682
12.3.5 Input Level Control/Status Register 3 (ICSR3) .................................................... 683
12.3.6 Software Port Output Enable Register (SPOER) .................................................. 685
12.3.7 Port Output Enable Control Register 1 (POECR1)............................................... 687
12.3.8 Port Output Enable Control Register 2 (POECR2)............................................... 688
12.4 Operation ........................................................................................................................... 693
12.4.1 Input Level Detection Operation........................................................................... 694
12.4.2 Output-Level Compare Operation ........................................................................ 695
12.4.3 Release from High-Impedance State..................................................................... 696
12.5 Interrupts............................................................................................................................ 697
Section 13 Compare Match Timer (CMT) ........................................................699
13.1 Features.............................................................................................................................. 699
13.2 Register Descriptions ......................................................................................................... 700
13.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 701
13.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 702
13.2.3 Compare Match Counter (CMCNT) ..................................................................... 704
13.2.4 Compare Match Constant Register (CMCOR) ..................................................... 704
13.3 Operation ........................................................................................................................... 705
13.3.1 Interval Count Operation ...................................................................................... 705
13.3.2 CMCNT Count Timing......................................................................................... 705
13.4 Interrupts............................................................................................................................ 706
13.4.1 Interrupt Sources and DMA Transfer Requests .................................................... 706
13.4.2 Timing of Compare Match Flag Setting ............................................................... 706
13.4.3 Timing of Compare Match Flag Clearing............................................................. 707
13.5 Usage Notes ....................................................................................................................... 708
13.5.1 Conflict between Write and Compare-Match Processes of CMCNT ................... 708
13.5.2 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 709
13.5.3 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 710
13.5.4 Compare Match between CMCNT and CMCOR ................................................. 710
Rev. 3.00 Jun. 18, 2008 Page xvii of xxiv