SH7206 Datasheet, PDF (866/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 A/D Converter (ADC)
Bit
11 to 8
Bit Name
TRGS[3:0]
Initial
Value
0000
7, 6
CKS[1:0] 01
R/W Description
R/W Timer Trigger Select
These bits enable or disable starting of A/D conversion
by a trigger signal.
0000: Start of A/D conversion by external trigger input
is disabled
0001: A/D conversion is started by conversion trigger
TRGAN from MTU2
0010: A/D conversion is started by conversion trigger
TRG0N from MTU2
0011: A/D conversion is started by conversion trigger
TRG4AN from MTU2
0100: A/D conversion is started by conversion trigger
TRG4BN from MTU2
0101: A/D conversion is started by conversion trigger
TRGAN from MTU2S
0110: Setting prohibited
0111: A/D conversion is started by conversion trigger
TRG4AN from MTU2S
1000: A/D conversion is started by conversion trigger
TRG4BN from MTU2S
1001: A/D conversion is started by ADTRG
1010 to 1111: Setting prohibited
R/W Clock Select
These bits select the A/D conversion time. Set the A/D
conversion time while A/D conversion is halted
(ADST = 0).
00: Conversion time = 138 states (maximum),
clock = Pφ/4
01: Conversion time = 274 states (maximum),
clock = Pφ/8
10: Conversion time = 546 states (maximum),
clock = Pφ/16
11: Setting prohibited
Rev. 3.00 Jun. 18, 2008 Page 842 of 1160
REJ09B0191-0300