SH7206 Datasheet, PDF (723/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
Section 13 Compare Match Timer (CMT)
This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.
The CMT has a 16-bit counter, and can generate interrupts at set intervals.
13.1 Features
• Independent selection of four counter input clocks at two channels
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.
• Selection of DMA transfer request or interrupt request generation on compare match by
DMAC setting
• When not in use, the CMT can be stopped by halting its clock supply to reduce power
consumption.
Figure 13.1 shows a block diagram of CMT.
CMI0
Pφ/8 Pφ/32 Pφ/128 Pφ/512
CMI1
Pφ/8 Pφ/32 Pφ/128 Pφ/512
Control circuit
Clock selection
Control circuit
Clock selection
Channel 0
Module bus
CMT
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
CMCOR: Compare match constant register
CMCNT: Compare match counter
CMI:
Compare match interrupt
Figure 13.1 Block Diagram of CMT
Channel 1
Bus
interface
Peripheral bus
Rev. 3.00 Jun. 18, 2008 Page 699 of 1160
REJ09B0191-0300