SH7206 Datasheet, PDF (266/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
4, 3
TRWL[1:0]* 00
R/W Number of Auto-Precharge Startup Wait Cycles
Specify the number of minimum auto-precharge
startup wait cycles as shown below.
• Cycle number from the issuance of the WRITA
command by this LSI until the completion of auto-
precharge in the SDRAM.
Equivalent to the cycle number from the issuance
of the WRITA command until the issuance of the
ACTV command. Confirm that how many cycles
are required between the WRITE command receive
in the SDRAM and the auto-precharge activation,
referring to each SDRAM data sheet. And set the
cycle number so as not to exceed the cycle number
specified by this bit.
• Cycle number from the issuance of the WRITA
command until the issuance of the PRE command.
This is the case when accessing another low
address in the same bank in bank active mode.
The setting for areas 2 and 3 is common.
00: No cycle
01: 1 cycle
10: 2 cycles
11: 3 cycles
2

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Jun. 18, 2008 Page 242 of 1160
REJ09B0191-0300