SH7206 Datasheet, PDF (376/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 8 Bus State Controller (BSC)
CKIO
BREQ
BACK
A25 to A0
D31 to D0
CSn
Other bus
contorol sigals
Figure 8.56 Bus Arbitration Timing (Clock Mode 7)
8.5.14 Others
(1) Reset
The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on
reset, all signals are negated and data output buffers are turned off regardless of the bus cycle state
after the internal reset is synchronized with the internal clock. All control registers are initialized.
In software standby, sleep, and manual reset, control registers of the bus state controller are not
initialized. At manual reset, only the current bus cycle being executed is completed. Since the
RTCNT continues counting up during manual reset signal assertion, a refresh request occurs to
initiate the refresh cycle.
(2) Access from the Side of the LSI Internal Bus Master
There are three types of LSI internal buses: a CPU bus, internal bus, and peripheral bus. The CPU
and cache memory are connected to the CPU bus. Internal bus masters other than the CPU and bus
state controller are connected to the internal bus. Low-speed peripheral modules are connected to
the peripheral bus. Internal memories other than the cache memory are connected bidirectionally
to the CPU bus and internal bus. Access from the CPU bus to the internal bus is enabled but
access from the internal bus to the cache bus is disabled. This gives rise to the following problems.
On-chip bus masters such as DMAC other than the CPU can access internal memory other than
the cache memory but cannot access the cache memory. If an on-chip bus master other than the
CPU writes data to an external memory other than the cache, the contents of the external memory
may differ from that of the cache memory. To prevent this problem, if the external memory whose
contents is cached is written by an on-chip bus master other than the CPU, the corresponding
cache memory should be purged by software.
In a cache-enabled space, if the CPU initiates read access, the cache is searched. If the cache stores
data, the CPU latches the data and completes the read access. If the cache does not store data, the
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