SH7206 Datasheet, PDF (791/1188 Pages) Renesas Technology Corp – 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 15 Serial Communication Interface with FIFO (SCIF)
(1) Transmit/Receive Formats
Table 15.11 lists the eight communication formats that can be selected in asynchronous mode. The
format is selected by settings in the serial mode register (SCSMR).
Table 15.11 Serial Communication Formats (Asynchronous Mode)
SCSMR Bits
CHR PE STOP 1
Serial Transmit/Receive Format and Frame Length
2 3 4 5 6 7 8 9 10 11 12
0 0 0 START
8-bit data
STOP
0 0 1 START
8-bit data
STOP STOP
0 1 0 START
8-bit data
P STOP
0 1 1 START
8-bit data
P STOP STOP
1 0 0 START
7-bit data
STOP
1 0 1 START
7-bit data
STOP STOP
1 1 0 START
7-bit data
P STOP
1 1 1 START
[Legend]
START: Start bit
STOP: Stop bit
P:
Parity bit
7-bit data
P STOP STOP
(2) Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCIF transmit/receive clock. The clock source is selected by the
C/A bit in the serial mode register (SCSMR) and bits CKE[1:0] in the serial control register
(SCSCR). For clock source selection, refer to table 15.10, SCSMR and SCSCR Settings and SCIF
Clock Source Selection.
When an external clock is input at the SCK pin, it must have a frequency equal to 16 times the
desired bit rate.
When the SCIF operates on an internal clock, it can output a clock signal on the SCK pin. The
frequency of this output clock is 16 times the desired bit rate.
Rev. 3.00 Jun. 18, 2008 Page 767 of 1160
REJ09B0191-0300